Active matrix liquid crystal panels have been in popular use for some time. An active matrix liquid crystal panel contains two transparent substrates sandwiching a liquid crystal layer. One of the transparent substrates is provided thereon with data signal lines (hereinafter, “data lines”) and scan signal lines crossing the data lines. Pixel electrodes, one for each intersection, are arranged to form a matrix. Each pixel electrode is connected to the data line running through the associated intersection via a TFT (thin film transistor) as a switching element. The gate terminal of the TFT is connected to the scan signal line running through that intersection. The other transparent substrate is provided thereon with an opposite electrode (common electrode) which is common to all the pixel electrodes.
The liquid crystal display device incorporating a liquid crystal panel configured as above includes gate drivers and source drivers as driver circuits to produce an image display on the liquid crystal panel. A gate driver, also termed a scan signal line driver circuit, is a driver circuit applying a scan signal to the scan signal lines to sequentially select the scan signal lines. A source driver, also termed a data signal line driver circuit or a video signal line driver circuit, is a driver circuit applying, to the data lines, a data signal by which data is written to pixel forming sections in the liquid crystal panel.
In this configuration, a common voltage Vcom is applied to the common electrode disposed opposite the pixel electrodes. Furthermore, a voltage corresponding to the pixel value assigned to each pixel electrode is applied between the pixel electrode and the opposite electrode. The liquid crystal layer changes its transmittance depending on the voltage applied, producing an image display on the crystal panel. In this process, the liquid crystal panel is A.C.-driven to prevent degradation of the liquid crystal material constituting the liquid crystal layer, In other words, the source driver outputs the data signal so that the (+)/(−) polarity of the voltage applied between the pixel electrode and the opposite electrode is inverted, for example, every frame.
Generally, in the active matrix liquid crystal panel, the transmittance of the liquid crystal layer is not completely symmetric with (+)/(−) data voltage even if the polarity of the data signal output of the source driver (applied voltage relative to the electric potential of the opposite electrode) is symmetric because of irregularities in the characteristics of the switching elements (e.g., TFTs) in individual pixels. This can be a cause for flickering of the display produced by the liquid crystal panel which is driven by inverting the (+)/(−) polarity of the voltage applied to the liquid crystal from one frame to the next (frame inversion drive scheme).
A driving scheme whereby the (+)/(−) polarity of the applied voltage is inverted for each horizontal scan signal line as well as for each frame is known to offer a solution to the flickering. Another known driving scheme inverts the (+)/(−) polarity of the voltage applied across the liquid crystal layer constituting the pixels for each scan signal line and data line as well as for each frame (dot inversion driving scheme).
FIG. 33 depicts a source driver output (image data) waveform when the display panel is being driven by a dot inversion driving scheme. In FIG. 33, a positive data signal Vpdata which is higher than the common voltage Vcom applied to the common electrode and a negative data signal Vndata which is lower than the common voltage Vcom are output alternately from one line to the next.
Meanwhile, the source driver is provided with numerous output buffers each connected to a data line to drive the load, i.e., the data line and the liquid crystal cell. When the source driver outputs the positive data signal Vpdata, the load charges through a current under a high potential voltage VDD; when the source driver outputs the negative data signal Vndata, the load discharges through a current under a low potential voltage VSS. The charge and discharge currents pass through the internal resistors of the output buffers in the source driver, increasing heat generation.
The heat generation inside the source driver occurs primarily in the output buffer sections. To lower the heat generation in the source driver, the heat generation in the output buffer sections, especially, at the output sections of the output buffers, should be reduced to a minimum. However, if the data signal voltage is flipped from the positive data voltage Vpdata to the negative data voltage Vndata and vice versa as illustrated in FIG. 33, the heat generation by the internal resistors in the output buffers increases with the difference between the positive data voltage Vpdata and the negative data voltage Vndata. In addition, the increased charge/discharge events result in increased power consumption.
Interlaced scanning (interlaced driving) methods have been proposed (for example, patent literature 1) as a prevention of the increase in power consumption. According to the interlaced scanning disclosed in patent literature 1, the scan signal lines for all the odd-numbered rows (or all the even-numbered rows) are first scanned, and those for the remaining even-numbered rows (or the remaining odd-numbered rows) are subsequently scanned.
FIG. 34 depicts a source driver output waveform for interlaced scanning. The polarity inverts when the scanning switches from the odd-numbered lines to the even-numbered lines because of the sequential scanning of the rows of pixels to which voltage of the same polarity is applied.
FIG. 35 depicts a source driver output waveform for interlaced driving when scanning is completed for one frame, that is, when scanning is completed for both the odd-numbered rows and the even-numbered rows. The source driver output waveform is similar to the one shown in FIG. 33 which was obtained by a dot inversion driving scheme. As can be appreciated from this, interlaced driving provides a means of inverting the polarity for each scan line and at the same time restricting polarity inversions, which in turn reduces charge/discharge events and restrains increase in power consumption.
Interlaced driving across the full screen of the liquid crystal panel as in patent literature 1 leads to flickering. To address this problem, driving methods have been proposed whereby the display section is divided into a plurality of regions in the column direction and interlaced scanning is carried out for each region (for example, patent literature 2).
FIG. 36 depicts a scan sequence disclosed in patent literature 2. The display section has eight lines of pixel electrodes and divides into regions 1 and 2. Interlaced driving is carried out for each region sequentially from two odd-numbered lines to two even-numbered lines. Data signals of different polarities are applied during the selection periods of regions 1 and 2. This restricts flickering.
The configuration of patent literature 2, however, entails problematic fine horizontal stripes, failing to deliver high quality images. As can be appreciated in FIG. 36, the fourth and fifth lines that are adjacent across the interface between regions 1 and 2 are contiguously scanned. Therefore, the potential difference between the data signal and the common voltage decreases due to the effect of coupling capacitance between the pixel electrodes as described in patent literature 3, making the fourth and fifth lines appear less intense than the other lines as illustrated in FIG. 37. The less intense, adjacent lines cause horizontal stripes to appear, degrading image quality.
Accordingly, patent literature 3 proposes an interlaced driving method whereby gate drivers are scanned in a reverse sequence. The following will describe the configuration disclosed in patent literature 3 in reference to FIGS. 38 to 40.
FIG. 38 depicts a configuration of a liquid crystal panel 101 and gate drivers 102 on which the driving method of patent literature 3 is implemented. The liquid crystal panel 101 includes 36 scan signal lines 1 to 36 and connects to two gate drivers 102.
FIG. 39 is a schematic illustration of the gate driver 102. The gate driver 102 has 18 output terminals O1 to O18 for scan signal outputs. The gate driver 102 also has four terminals SP1, SP2, CLK, and OS. The terminal CLK is an input terminal for an operating clock. The terminal SP1 is an input terminal for a start signal SP. As a HIGH pulse is received at the terminal SP1, the gate driver 102 outputs a scan signal in synchronism with the operating clock CLK received at the terminal CLK. The terminal SP2 is an output terminal for the start signal SP. The terminal SP2 of a gate driver 102 is cascaded to the terminal SP1 of the succeeding-stage gate driver 102 as illustrated in FIG. 38.
The terminal OS is a function switching terminal for the gate driver 102. When the input signal at the terminal OS is HIGH, the scan signal is output first from odd-numbered output terminals (O1, O3, O5, . . . , and O17) and subsequently from even-numbered output terminals (O2, O4, O6, . . . , and O18). When the input signal at the terminal OS is LOW, the scan signal is output first from even-numbered output terminals (O2, O4, O6, . . . , and O18) and subsequently from odd-numbered output terminals (O1, O3, O5, . . . , and O17).
The liquid crystal panel 101 connects to two gate drivers 102 as illustrated in FIG. 38. For convenience, the gate driver 102 in the preceding stage will be referred to as the gate driver 102a, and the one in the succeeding stage as the gate driver 102b. The output terminals O1 to O18 of the gate driver 102a are connected respectively to the scan signal lines 1 to 18 of the liquid crystal panel 101. The output terminals O1 to O18 of the gate driver 102b are connected to respectively to the scan signal lines 19 to 36 of the liquid crystal panel 101. The terminal SP1 of the gate driver 102a receives the incoming start signal SP from a controller (not shown). The terminal SP2 of the gate driver 102a is connected to the terminal SP1 of the gate driver 102b. The controller (not shown) supplies the operating clock CLK at the terminals CLK of the gate drivers 102a and 102b. The input at the terminal OS of the gate driver 102a is fixed to HIGH, whilst the input at the terminal OS of the gate driver 102a is fixed to LOW.
FIG. 40 depicts scan signal outputs (driving waveforms) from the gate drivers 102a and 102b. 
As the start signal SP is supplied at the terminal SP1 of the gate driver 102a, the gate driver 102a detects a HIGH input at the terminal SP1 and starts driving the scan signal lines on a rise of the operating clock CLK being supplied at the terminal CLK. Since the input at the terminal OS of the gate driver 102a is HIGH, the output terminal O1 first goes HIGH. On a next rise of the operating clock CLK, the output terminal O1 goes LOW, and at the same time the output terminal O3 goes HIGH. In this manner, the odd-numbered output terminals O1, O3, . . . , and O17 sequentially output a HIGH pulse.
Next, the output terminal O2 goes HIGH. On a next rise of the operating clock CLK, the output terminal O2 goes LOW, and at the same time the output terminal O4 goes HIGH. In this manner, the even-numbered output terminals O2, O4, . . . , and O18 sequentially output a HIGH pulse. In addition, when the output terminal O18 goes HIGH, the terminal SP2 goes HIGH.
The terminal SP2 of the gate driver 102a is connected to the terminal SP1 of the gate driver 102b. Therefore, when the terminal SP2 of the gate driver 102a goes HIGH, the terminal SP1 of the gate driver 102b goes HIGH. Accordingly, the gate driver 102b starts driving the scan signal lines on a next rise of the operating clock CLK.
Since the input at the output terminal OS of the gate driver 102b is LOW, the output terminal O2 first goes HIGH unlike the operation of the gate driver 102a. On a next rise of the operating clock CLK, the output terminal O2 goes LOW, and at the same time the output terminal O4 goes HIGH. In this manner, the even-numbered output terminals O2, O4, . . . , and O18 sequentially output a HIGH pulse.
Next, the output terminal O1 goes HIGH. On a next rise of the operating clock CLK, the output terminal O1 goes LOW, and at the same time the output terminal O3 goes HIGH. In this manner, the odd-numbered output terminals O1, O3, . . . , and O17 output a HIGH pulse. Simultaneously, the terminal SP2 also goes HIGH.
Hence, the configuration can implement the driving method whereby the gate driver 102a carries out interlaced driving on the scan signal lines 1 to 18 of the liquid crystal panel 101 shown in FIG. 38 by first scanning the odd-numbered lines and subsequently scanning the even-numbered lines, and the gate driver 102b carries out interlaced driving on the scan signal lines 19 to 36 by first scanning the even-numbered lines and subsequently scanning the odd-numbered lines. By following the reverse interlaced driving scan sequences in the gate drivers 102a and 102b in this manner, the image quality degradation which occurs in the configuration disclosed in patent literatures 1 and 2 can be prevented as described in patent literature 3.
Another problem is that if the power supply for the liquid crystal panel is turned off when the pixel capacitance of a TFT is holding electric charge, the charge may be held and produce an afterimage on the display screen for an extended period of time, degrading display quality. Patent literature 4, as an example, proposes a solution to the problem whereby the afterimage is erased in a short period of time by holding the outputs of scan signal line driver circuits simultaneously at an active level for a predetermined period of time when the power supply is turned off.